Carsten 'JC' Jaeck
id: 1751039
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| THE SKY IS THE LIMIT aktueller Overclocking stand 24.12.2009 Ratio CMOS Setting: 8 FSB Frequency: 500 CPU Clock Skew: Auto NB Clock Skew: Auto FSB Strap to North Bridge: 333 DRAM Frequency: DDR2-1002Mhz (1:1) DRAM CLK Skew on Channel A1: Auto DRAM CLK Skew on Channel A2: Auto DRAM CLK Skew on Channel B1: Auto DRAM CLK Skew on Channel B2: Auto DRAM Timing Control: Manual 1st Information: CAS# Latency: 5 DRAM RAS# to CAS# Delay: 5 DRAM RAS# Precharge: 5 DRAM RAS# Activate to Precharge: 15 RAS# to RAS# Delay: 3 Row Refresh Recycle Time: 55 Write Recovery Time: Auto Read to Precharge Time: Auto 2nd Information: Read to Write Delay (S/D): Auto Write to Read Delay (S): Auto Write to Read Delay (D): Auto Read to Read Delay (S): Auto Read to Read Delay (D): Auto Write to Write Delay (S): Auto Write to Write Delay (D): Auto 3rd Information: Write to PRE Delay: Auto Read to PRE Delay: Auto PRE to PRE Delay: Auto All PRE to ACT Delay: Auto All PRE to REF Delay: Auto DRAM Static Read Control: Disabled DRAM Read Training: Disabled MEM. OC Charger: Enabled Ai Clock Twister: Auto Ai Transaction Booster: Enabled Common Performance Level: 10 Pull-in of CHA PH1: Disabled Pull-in of CHA PH2: Disabled Pull-in of CHA PH3: Disabled Pull-in of CHB PH1: Disabled Pull-in of CHB PH2: Disabled Pull-in of CHB PH3: Disabled PCIE Frequency: 100 CPU Voltage: 1.40625 CPU PLL Voltage: 1.51325 FSB Termination Voltage: 1.25900 DRAM Voltage: 1.97225 North Bridge Voltage: 1.25900 South Bridge 1.5 Voltage: 1.51325 South Bridge 1.1 Voltage: 1.11325 CPU GTL Reference (0): Auto CPU GTL Reference (1): Auto CPU GTL Reference (2): Auto CPU GTL Reference (3): Auto NB GTL Reference: Auto DDR2 ChA Reference Voltage: Auto DDR2 ChB Reference Voltage: Auto North Bridge DDR Reference: Auto CPU Configuration: Ratio CMOS Setting: 8 C1E Support: Disabled Max CPUID Value Limit: Disabled Intel Virtualization Tech: Disabled CPU TM Function: Enabled Execute Disable Bit: Enabled Load-Line Calibration: Disabled CPU Spread Spectrum: Disabled PCIE Spread Spectrum: Disabled |